Open
Bug 1258488
Opened 9 years ago
Updated 2 years ago
ARM barriers should be restricted to using the Inner Sharable domain
Categories
(Core :: JavaScript Engine: JIT, defect, P5)
Tracking
()
NEW
People
(Reporter: lth, Unassigned)
References
(Blocks 1 open bug)
Details
I was looking at Apple's Clang code at one point and observing that the barriers were being emitted only for the "inner sharable" domain, and wondering whether that would be a valid optimization also on non-Apple devices. The answer appears to be yes. This is a note tucked away in the ARM v7 reference manual:
"This architecture is written with an expectation that all processors using the same operating system or hypervisor are in the same Inner Shareable shareability domain."
Switching to DMB ISH and DMB ISHST is not much work - a conditional in the MacroAssembler. Some risk, of course, if I have interpreted that quote incorrectly...
Reporter | ||
Comment 1•9 years ago
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In a conversation, JF Bastien noted that DMB ISHST (which is emitted by Clang on some Apple chips) is probably not correct in general on ARM for the barriers we need (though it might be appropriate for rel_acq).
Reporter | ||
Updated•8 years ago
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Component: JavaScript Engine → JavaScript Engine: JIT
Priority: -- → P5
Reporter | ||
Updated•8 years ago
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No longer blocks: shared-array-buffer
Updated•2 years ago
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Severity: normal → S3
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Description
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