Closed
Bug 643109
Opened 14 years ago
Closed 14 years ago
TI+JM: add JSOP_RSH to jsop_bitop
Categories
(Core :: JavaScript Engine, defect)
Core
JavaScript Engine
Tracking
()
RESOLVED
FIXED
People
(Reporter: jandem, Assigned: jandem)
References
Details
Attachments
(1 file)
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(deleted),
patch
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bhackett1024
:
review+
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Details | Diff | Splinter Review |
JSOP_RSH has its own function because IIRC (?) it had to support double operands. Now that jsop_bitop (used for the other binary bitwise ops) also supports double operands, we can remove the special treatment for JSOP_RSH.
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Assignee | |
Updated•14 years ago
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Assignee: general → jandemooij
Status: NEW → ASSIGNED
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Assignee | |
Comment 1•14 years ago
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Removes about 100 lines of code.
Attachment #521579 -
Flags: review?(bhackett1024)
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Comment 2•14 years ago
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Comment on attachment 521579 [details] [diff] [review]
Patch
>-RegisterID
>-mjit::Compiler::rightRegForShift(FrameEntry *rhs)
>-{
>-#if defined(JS_CPU_X86) || defined(JS_CPU_X64)
>- /*
>- * Gross: RHS _must_ be in ECX, on x86.
>- * Note that we take this first so that we can't up with other register
>- * allocations (below) owning ecx before rhs.
>- */
>- RegisterID reg = JSC::X86Registers::ecx;
>- if (!rhs->isConstant())
>- frame.copyDataIntoReg(rhs, reg);
>- return reg;
>-#else
>- if (rhs->isConstant())
>- return frame.allocReg();
>- return frame.copyDataIntoReg(rhs);
>-#endif
>-}
Isn't this code still necessary? How do we ensure the RHS in is in ECX for an 'x >> y' op?
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Assignee | |
Comment 3•14 years ago
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(In reply to comment #2)
> Comment on attachment 521579 [details] [diff] [review]
>
> Isn't this code still necessary? How do we ensure the RHS in is in ECX for an
> 'x >> y' op?
jsop_bitop calls tempRegInMaskForData(rhs, Registers::maskReg(JSC::X86Registers::ecx)) for all shift ops.
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Updated•14 years ago
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Attachment #521579 -
Flags: review?(bhackett1024) → review+
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Comment 4•14 years ago
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Status: ASSIGNED → RESOLVED
Closed: 14 years ago
Resolution: --- → FIXED
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Description
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